/*
 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 
 *  
 * SPDX-License-Identifier: Apache-2.0.
 * 
 * @Date: 2021-08-23 16:23:12
 * @LastEditTime: 2021-08-26 10:52:25
 * @Description:  This files is for 
 * 
 * @Modify History: 
 *  Ver   Who        Date         Changes
 * ----- ------     --------    --------------------------------------
 */
#include "ft_assert.h"
#include "gmac.h"
#include "gmac_hw.h"

#define GMAC_TRUE_FALSE_STR(x) ((x)?"TRUE":"FALSE")

/**
 * @name: GmacCfgInitialize
 * @msg: init gmac configs
 * @return {*}
 * @param {GmacCtrl} *pCtrl
 * @param {GmacConfig} *pConfig
 */
u32 GmacCfgInitialize(GmacCtrl *pCtrl, const GmacConfig *pConfig)
{
    FT_ASSERTZERONUM(pCtrl && pConfig);
    pCtrl->config = *pConfig;
    pCtrl->isReady = FT_COMPONENT_IS_READY;

    return GMAC_SUCCESS;
}

/**
 * @name: GmacProbe
 * @msg: probe gmac ctrl status
 * @return {*}
 * @param {GmacCtrl} *pCtrl
 */
void GmacProbe(const GmacCtrl *pCtrl)
{
    FT_ASSERTVOID(pCtrl);
    u32 regVal;

    GMAC_INFO("gmac-%ld at %p", pCtrl->config.instanceId, pCtrl->config.baseAddr);
    regVal = GMAC_READ_REG(pCtrl, GMAC_CONF_OFFSET);
    GMAC_INFO(" ctrl reg: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_GMII_ADDR_OFFSET);
    GMAC_INFO(" gmii addr reg: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_INTR_STATUS_OFFSET);
    GMAC_INFO(" intr status reg: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_INTR_MASK_OFFSET);
    GMAC_INFO(" intr mask reg: 0x%lx", regVal);
    GMAC_INFO(" mac addr: [%lx:%lx]", 
             GMAC_MAC_ADDR0_UPPER16BIT_A & GMAC_READ_REG(pCtrl, GMAC_MAC_ADDR0_UPPER16BIT_OFFSET),
             GMAC_MAC_ADDR0_LOWER32BIT_A & GMAC_READ_REG(pCtrl, GMAC_MAC_ADDR0_LOWER32BIT_OFFSET));
    regVal = GMAC_READ_REG(pCtrl, GMAC_MAC_PHY_STATUS);
    GMAC_INFO(" phy status reg: 0x%lx", regVal);

    GMAC_INFO("dma ctrl");
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_BUS_MODE_OFFSET);
    GMAC_INFO(" bus mode: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_RX_LIST_BASE_OFFSET);
    GMAC_INFO(" first rx desc addr: 0x%lx", 
             (GMAC_DMA_RCV_BASE_ADDR_START_REC_LIST & regVal) >> 4);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_TX_LIST_BASE_OFFSET);
    GMAC_INFO(" first tx desc addr: 0x%lx", 
             (GMAC_DMA_TX_BASE_ADDR_START_TRA_LIST & regVal) >> 4);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_STATUS_OFFSET);
    GMAC_INFO(" status: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_OP_OFFSET);
    GMAC_INFO(" op mode: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_INTR_OFFSET);
    GMAC_INFO(" intr enable: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_HOST_TX_DESC_OFFSET);
    GMAC_INFO(" cur tx desc addr: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_HOST_RX_DESC_OFFSET);
    GMAC_INFO(" cur rx desc addr: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_HOST_TX_BUF_ADDR_OFFSET);
    GMAC_INFO(" cur tx buff addr: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_HOST_RX_BUF_ADDR_OFFSET);
    GMAC_INFO(" cur rx buff addr: 0x%lx", regVal);
    regVal = GMAC_READ_REG(pCtrl, GMAC_DMA_HW_FUNC_OFFSET);
    GMAC_INFO(" hardware func: 0x%lx", regVal);

    GMAC_INFO("");
    GMAC_INFO("dma desc info");
    GMAC_INFO(" tx desc: %p, size: %ld, cur idx: %ld", 
            &pCtrl->txRing, pCtrl->txRing.descMaxNum, pCtrl->txRing.descIdx);
    GMAC_INFO(" rx desc: %p, size: %ld, cur idx: %ld", 
            &pCtrl->rxRing, pCtrl->rxRing.descMaxNum, pCtrl->rxRing.descIdx);
    GMAC_INFO(" tx buf: %p", pCtrl->txRing.descBufBase);
    GMAC_INFO(" rx buf: %p", pCtrl->rxRing.descBufBase);

    (void)regVal;
}